1. Field of the Invention
The present invention relates to a chip package structure and fabricating method thereof, and more particularly, to an embedded chip package structure and fabricating method thereof.
2. Description of Related Art
With continuous innovation in electronic technologies in recent years, more personalized and functionally improved hi-tech electronic products continue to appear in the market. Moreover, the upcoming trend in design is to produce lighter and more compact products. In general, a circuit substrate is disposed inside these electronic products. The circuit substrate carries a single chip or multiple chips to serve as the data processing unit of the electronic product. However, disposing one or more chips on the circuit substrate often increases the carrying surface area. Therefore, embedding the chips inside the circuit substrate has become a critical technique at the moment.
FIG. 1 is a schematic cross-sectional view of a conventional embedded chip package structure. As shown in FIG. 1, the embedded chip package structure 30 includes a substrate 300, a plurality of chips 310, a dielectric layer 330, an oxidation-resistant layer 360 and a solder mask layer 370. The chips 310 are disposed on the substrate 300, and the dielectric layer 330 is formed over the substrate 300 to cover the chips 310. In addition, the bonding pad 320 of each of the chips 310 is electrically connected to a conductive hole 340, and the conductive hole 340 is electrically connected to a corresponding conductive plug 350 to form an embedded chip package structure 30.
In the foregoing embedded chip package structure 30, the chips 310 are arranged to be disposed on the same plane. To increase the number of chips 310 in the package structure 30, the area of the substrate 300 must be increased correspondingly. With this constraint, if the performance of the embedded chip package structure needs to improve, the volume of the embedded chip package structure must be increased to accommodate more chips. However, this is not a good option considering the current trend of product streamlining and miniaturization. Conversely, if the embedded chip package structure is miniaturized to meet the current trend, the number of chips that can be packed inside the structure is reduced so that the performance of the embedded chip package structure is lowered.